Integration system via metal oxide conversion

ABSTRACT

A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfO x  and a ZrO x .

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to microelectronicintegrated circuits, and more particularly to ametal-oxide-semiconductor field-effect transistor (MOSFET) device and amethod for producing the same.

[0003] 2. Description of the Related Art

[0004] Advanced generations of microelectronic integrated circuits usemetal-oxide-semiconductor field-effect transistor (MOSFET) devices withgate insulator materials having a dielectric constant greater than thatof silicon dioxide and silicon-oxy-nitride materials. HfO_(x) andZrO_(x) materials have been proposed as high-k gate insulator materials.In fact, it is desirable to incorporate these gate insulator materialsinto a complementary n-channel and p-channel MOSFET (CMOS) process.Moreover, these high-k materials have been used as an etch-stop film,wherein after the etching occurs, the stop film in the connect area ofthe MOSFET device is converted to metal by a specific annealing process.

[0005] For example, in studies examining the effects of ZrO₂ and Zrsilicate (Zr₂₇Si₁₀O₆₃) gate dielectrics deposited on silicon substrates,these high-k materials showed excellent equivalent oxide thicknesses(EOT) of 9.9 angstroms (ZrO₂) and 9.6 angstroms (Zr₂₇Si₁₀O₆₃), with verylow leakage currents of 20 mA/cm² and 23 mA/cm², respectively (C. H. Leeet al., “MOS Characteristics of Ultra Thin Rapid Thermal CVD ZrO₂ and ZrSilicate Gate Dielectrics,” IEEE Tech. Dig., 2000, the completedisclosure of which is herein incorporated by reference). In anotherstudy, HfO₂ demonstrated equally as well, having an EOT of 10.4angstroms and a leakage current of 0.23 mA/cm² (S. J. Lee et al., “HighQuality Ultra Thin CVD HfO₂ Gate Stack with Poly-Si Gate Electrode,”IEEE Tech. Dig., 2000, the complete disclosure of which is hereinincorporated by reference).

[0006] However, due to the ever-increasing performance required ofMOSFET devices, and the lack of a conventional device capable of meetingperformance specifications, there is a need for a new and improvedstructure and method of manufacturing a high-performance MOSFET devicecapable of achieving present and future technological specifications forintegrated circuit technology.

SUMMARY OF THE INVENTION

[0007] The present invention has been devised to provide a structure andmethod for manufacturing a high performance MOSFET device. The presentinvention provides a structure which integrates a combination of a highdielectric constant gate insulator and a low-resistance metal silicidesource/drain region in a self-aligned manner without incurring extraprocessing cost. The present invention provides a method which reducesthe number of processing steps used to manufacture a MOSFET devicehaving a high-dielectric constant gate insulator and a low-resistancesilicide (salicide) source/drain region relative to conventional MOSFETdevices. The present invention provides a method for converting a metaloxide thin film to a metallic thin film in selected source/drain regionssuch that a subsequent annealing process will convert the metallic filmto a silicide (salicide) film in order to improve the device seriesresistance.

[0008] There is provided, according to one aspect of the invention a newself-aligned and low-cost silicidation process. While forming a MOSdevice with a high-k gate dielectric using a proper metal oxide such asHfO_(x) or ZrO_(x), the remaining high-k dielectric in the source/drainregions exposed to the air are converted into metal. One feature of thepresent process is the ability to block the high-k dielectric, whichdirectly contacts the gate conductor, by using a cap dielectric layer. Asubsequent silicidation process forms silicide alloy only in thesource/drain region to reduce device series resistance. By controllingthe metal conversion processing step, the overlap capacitance due to thegate and source/drain overlap with the high-k dielectric is alsominimized. The high-k dielectric on top of the insulating substrate canalso be used to form resistors. In short, a low-cost fabrication methodto integrate very high-performance active and passive devices is taughtin this disclosure.

[0009] Specifically, according to the present invention, a transistordevice, and method of forming the same, is disclosed comprising forminga source region, a drain region, and a trench region in a substrate.Then, a first insulator is formed over the substrate. Next, a gateelectrode is formed above the first insulator. Upon completion of thisstep, a pair of insulating spacers are formed adjoining the electrode.Next, a portion of the first insulator is converted into a metallicfilm. Then, at least a portion of the metallic film is converted intoone of a silicide and a salicide film.

[0010] The method further comprises forming an interconnect region abovethe trench region and forming an etch stop layer above the firstinsulator, the trench region, the gate electrode, and the pair ofinsulating spacers. Next, a second insulator is formed above the etchstop layer, and finally, contacts are formed in the second insulator.The first insulator comprises a metal oxide material, and specifically,comprises one of a HfO_(x) and a ZrO_(x).

[0011] In the step of converting a portion of the first insulator into ametallic film, the portion of the first insulator comprises a regionabove the source and the drain regions of the substrate. Moreover, thestep of converting the metallic film into one of a silicide and asalicide film occurs in a region above the source and drain regions ofthe substrate. Furthermore, the step of converting a portion of thefirst insulator into a metallic film occurs by annealing in a reducingambient environment. Additionally, the step of converting the metallicfilm into one of a silicide and a salicide film occurs by one of anannealing process and a wet etching process.

[0012] Also, a transistor device is disclosed comprising a substratewith a metal oxide film above the substrate, a gate electrode above themetal oxide film, and spacers adjacent to the gate electrode. The metaloxide film has a first region below the gate electrode and secondregions not protected by the gate electrode. Moreover, the secondregions have a reduced oxygen content when compared to the first region.Also, the second regions extend partially under the spacers. Thetransistor device in the second portions includes a silicide region andfurther comprises a source and drain region in the substrate below thesecond regions. Finally, the first region comprises a gate insulator.

[0013] According to the present invention, the performance of a MOSFETdevice is influenced by the dielectric properties of the thin gateinsulator, and the series resistance of the source/drain region of thetransistor. Additionally, the device's transconductance is increased, bythe introduction of a high-dielectric constant gate insulator.

[0014] Moreover, according to the present invention, the seriesresistance of the source/drain region of the transistor is reduced bythe introduction of a metal silicide on the surface of the source/drainregion. Also, the gate to source/drain overlap capacitance is reduced byminimizing the overlap area using a self-aligned processing scheme.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The invention will be better understood from the followingdetailed description of preferred embodiments of the invention withreference to the drawings, in which:

[0016]FIG. 1 is a cross-sectional schematic diagram of a partiallycompleted metal-oxide-semiconductor field-effect transistor deviceaccording to the present invention;

[0017]FIG. 2 is a cross-sectional schematic diagram of a partiallycompleted metal-oxide-semiconductor field-effect transistor deviceaccording to the present invention;

[0018]FIG. 3 is a cross-sectional schematic diagram of a partiallycompleted metal-oxide-semiconductor field-effect transistor deviceaccording to the present invention;

[0019]FIG. 4 is a cross-sectional schematic diagram of a partiallycompleted metal-oxide-semiconductor field-effect transistor deviceaccording to the present invention;

[0020]FIG. 5 is a cross-sectional schematic diagram of a partiallycompleted metal-oxide-semiconductor field-effect transistor deviceaccording to the present invention;

[0021]FIG. 6 is a cross-sectional schematic diagram of a completedmetal-oxide-semiconductor field-effect transistor device according tothe present invention;

[0022]FIG. 7 is a flow diagram illustrating a preferred method of theinvention; and

[0023]FIG. 8 is a flow diagram illustrating a preferred method of theinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0024] As previously mentioned, there is a need for an improvedstructure and method for manufacturing a high performance MOSFET devicecapable of achieving present and future technological specifications forintegrated circuit technology. According to the present invention, a newand improved structure and method for manufacturing a high performanceMOSFET device is disclosed.

[0025] Referring now to the drawings, and more particularly to FIGS. 1through 8, there are shown preferred embodiments of the method andstructures according to the present invention. Specifically, FIGS. 1through 5 illustrate a partially completed metal-oxide-semiconductorfield-effect transistor device 1 according to the present invention, andFIG. 6 illustrates a completed metal-oxide-semiconductor field-effecttransistor device 1 according to the present invention. The preferredmethods of the present invention are shown in FIGS. 7 and 8.

[0026]FIG. 1 shows a partially completed MOSFET device 1 comprising asubstrate 10, a shallow trench isolation (STI) region 20 and asource/drain diffusion region 40 formed in the substrate 10, a gateinsulator 25 over the STI region 20, the substrate 10, and thesource/drain diffusion region 40, a gate electrode 30 positioned overthe gate insulator 25, and an insulator layer 50 over the gate electrode30 and the gate insulator 25.

[0027] The substrate 10 preferably includes an impurity doping well,such as a silicon wafer, or silicon-on-insulator wafer. The STI region20 is formed by conventional processing such as photolithographypatterning, dry etching to a depth below the semiconductor junctionsformed in subsequent processing steps as is known to those skilled inthe art, oxide fill deposition, and planarization such as chemicalmechanical polish (CMP).

[0028] The gate insulator 25 comprises a high dielectric constantmaterial such as HfO_(x) or ZrO_(x), and is formed by a chemical vapordeposition (CVD) or physical sputtering to an equivalent oxide thickness(EOT) of 1 nm-5 nm. The gate electrode material 30 preferably comprisesLPCVD polysilicon or TiN having a thickness of 5 nm-100 nm. Moreover,the gate electrode 30 is patterned by conventional lithography and dryetching techniques. Furthermore, the source/drain extension diffusionregion 40 is formed by ion implantation.

[0029]FIG. 2 shows the device 1 after it has undergone an etchingprocess, wherein the insulator layer 50 is etched to form a pair of gatesidewall spacers 50 on two sides of the gate electrode 30. The gateelectrode 30 and spacers 50 form a protective cap. The spacers 50 arepreferably formed by low-pressure chemical vapor deposition (LPCVD) ofSiN to a thickness of 2 nm to 20 nm, and anisotropic dry etching such asflourine-containing plasma which is selective to the high-k gatedielectric 25 but not selective to the layer 50. That is, the etchingprocess removes the layer 50 from above the gate electrode 30, and fromall other areas above the high-k dielectric layer 25 except from thesidewall spacer regions 50 adjoining either side of the gate electrode30. This does not substantially affect the dielectric 25 or gate 30.Thus, the etching process does not remove the gate electrode 30 or thehigh-k dielectric layer 25. Thus, according to the present invention,the layer 50 on top of the source/drain area is removed, and theunderlying high-k dielectric is exposed.

[0030]FIG. 3 illustrates the conversion of the gate insulator 25 to ahighly conductive metallic material 90 in regions not blocked by theprotective cap formed by the gate electrode 30 and sidewall spacers 50.Furthermore, a deep high doping implant source/drain region 60 is alsoshown embedded in the substrate 10. The conversion preferably consistsof a thermal annealing process in a reducing ambient such as H₂, and/oran annealing process in a vacuum to drive the oxygen out of the metaloxide film, i.e., to reduce the metal oxide. This process minimizes theoverlap capacitance of the device 1.

[0031] The overlap capacitance is best illustrated in FIGS. 3-6, whereit is seen that the portions of the high-k dielectric 25 extending underthe spacers 50 (both sides) creates an overlap in the capacitance,thereby slowing the switching effects of the device 1. In other words,if a metal were formed beneath the spacers, a capacitor structure wouldexist that would slow the speed at which the transistor switched.Theoretically, the overlap capacitance can be eliminated by removing allexcess high-k dielectric material 25 from underneath the spacers 50,thus only having the high-k dielectric positioned underneath the gateelectrode 30. However, this could possibly lead to the metallic film 90coming into contact with the gate electrode 30, which would cause devicefailure. Thus, the high-k dielectric material 25 is extended below thespacers 50 as a factor of safety. However, contrary to conventionaldevices, the present invention reduces the overlap capacitance in thedevice 1 by controlling the metal conversion step (conversion of high-kdielectric material 25 to the metal oxide 90) very precisely with thecap (spacers 50 and gate 30). Thus, since the positions of the metallicand insulating portions of the layer 25 are self-aligned and preciselycontrolled with the cap (spacers 50 and gate 30), a capacitor is notcreated under the spacers 50 and overlap capacitance is avoided.

[0032]FIG. 4 shows the formation of a self-aligned silicide (salicide)100 from the conversion of at least a portion of the metallic material(metal oxide) 90 by an additional thermal step which causes a metalalloy 100 to form on the underlying substrate layer 10. The metal oxide90 conversion to metal 100 occurs by annealing in a reducing ambient H₂environment. Moreover, the salicide 100 is formed by a wet etchingprocesses as well. Thus, for example a metal oxide 90 comprising HfO_(x)is converted to a Hf metal 100, or similarly, a metal oxide 90comprising ZrO_(x) is converted to a Zr metal 100 in this process.

[0033] The high-k material 90 on top of the shallow trench isolationregion, however, may be used to form resistor components via extramasking steps. The sheet resistance of an annealed high-k dielectric ontop of an insulating substrate can be in the range of kilo-ohm/squareunits to Mega-ohm/square units. These resistors are valuable for manyapplications. For example, they can be used to form a pull-up device fora SRAM cell, a resistor divider, or analog RC component. Achlorine-containing isotropic etch such as a wet solution is used toselectively remove the non-alloyed metallic material from over the STI20. Because this is a self-aligning process, at least one metaldeposition process is eliminated. Therefore, the present method reducesthe fabrication cost of the device.

[0034] In FIG. 5, a cross section of the MOSFET device 1 is shown with aliner material 130 such as LPCVD SiN of thickness 2 nm to 30 nmdeposited over the structure including the alloy 100, gate electrode 30,sidewall spacers 50, and the STI region 20. The liner material 130serves as an etch stop layer for subsequent processing steps. Aninterlevel dielectric 150 such as boron and phosphorus doped glass(BPSG) is deposited over the liner material 130. Also, a contact via200, which is formed by conventional lithographic, dry etch, metaldeposition, and planarization techniques, is formed in the interleveldielectric 150, and connects to the alloy 100.

[0035]FIG. 6 illustrates the inventive device 1 including a localinterconnect region 210 over the STI region 20. The local interconnectregion 210 is delineated by additional masking levels during thesalicide formation process. Moreover, the interconnect 210 may beadapted to bridge between diffusion regions without the need to use thediffusion contact 200. The interconnect region 210 comprises themetallic material (metal oxide) 90.

[0036] Subsequent formation of interconnects (not shown) can proceedwith conventional processing. It will be obvious to those skilled in theart that complementary n-channel and p-channel MOSFET (CMOS) devices canbe produced using the method and structure as taught in this inventionby application of impurity doping such as ion implantation to selectedregions of the structure and substrate.

[0037]FIG. 7 illustrates a flow diagram of the entire process of forminga high performance MOSFET device 1 according to the present invention.The method comprises forming 700 a source region and drain region 40,and a trench region 20 in a substrate 10. Then, a first insulator 25 isformed 710 over the substrate 10. Next, a gate electrode 30 is formed720 above the first insulator 25. After this, a dielectric layer 50 isdeposited 730 above the gate electrode 30 and the first insulator 25.Upon completion of this step, a pair of insulating spacers 50 are formed740 adjoining the electrode 30. Also, an additional high dopant implantsource and drain region 60 may be formed 750 in the substrate 10. Next,a portion of the first insulator 90 is converted 760 into a metallicfilm 90. Then, the metallic film 90 is converted 770 into one of asilicide and a salicide film 100.

[0038] The method further comprises forming 780 an interconnect region210 above the trench region 20 and forming 790 an etch stop layer 130above the first insulator 25, the trench region 20, the gate electrode30, and the pair of insulating spacers 50. Next, a second insulator 150is formed 795 above the etch stop layer 130, and finally, contacts 200are formed 799 in the second insulator 150.

[0039] As shown in FIG. 8, according to the present invention, forhigh-k CMOS gate dielectric 25 formation using Hr-oxide and Zr-oxidematerials includes a final HF (hydrogen fluoride) cleaning process 800for a hydrogen-terminated surface. Then, a thermal nitridation process810 occurs such as a high-temperature step in a NH₃-containing ambientto form a silicon nitride (and/or oxynitride) layer of 5 angstroms to 15angstroms, and preferably 8 angstroms. Next, a CVD process 820 occurs(atomic layer CVD or metal-organic CVD) of the metal oxide materials.Finally, a gate electrode deposition 830 occurs such as a CVD ofsilicon, or optionally with a TiN or other metallic barrier before thegate polysilicon deposition.

[0040] The present invention provides for a new self-aligned andlow-cost silicidation process. While forming a MOS device with a high-kgate dielectric using a proper metal oxide such as HfO_(x) or ZrO_(x),the remaining high-k dielectric in the source/drain regions exposed tothe air are converted into metal. One feature of the present process isthe ability to block the high-k dielectric, which directly contacts thegate conductor, by using dielectric spacers 50. A subsequentsilicidation process forms silicide alloy only in the source/drainregion to reduce device series resistance. By controlling the metalconversion processing step, the overlap capacitance due to the gate andsource/drain overlap with the high-k dielectric is also minimized. Thehigh-k dielectric on top of the insulating substrate can also be used toform resistors. In short, a low-cost fabrication method to integratevery high-performance active and passive devices is taught in thisdisclosure.

[0041] While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

What is claimed is:
 1. A transistor device comprising: a substrate; ametal oxide film above said substrate; a gate electrode above said metaloxide film; and spacers adjacent said gate electrode, wherein said metaloxide film has a first region below said gate electrode and saidspacers, and second regions not protected by said gate electrode or saidspacers, and wherein said second regions have a reduced oxygen contentwhen compared to said first region.
 2. The transistor device of claim 1,wherein said metal oxide film comprises one of a HfO_(x) and a ZrO_(x).3. The transistor device in claim 1, wherein said second regions includea silicide region.
 4. The transistor device in claim 1, furthercomprising source and drain regions in said substrate below said secondregions.
 5. The transistor device in claim 1, wherein said first portioncomprises a gate insulator.
 6. A transistor device comprising: asubstrate; a metal oxide film above said substrate; and a gate electrodeabove said metal oxide film, wherein said metal oxide film has a firstregion below said gate electrode and second regions not protected bysaid gate electrode, wherein said second regions have a reduced oxygencontent when compared to said first region.
 7. The transistor device inclaim 6, wherein said second regions include a silicide region.
 8. Thetransistor device in claim 6, further comprising source and drainregions in said substrate below said second regions.
 9. The transistordevice in claim 6, wherein said first region comprises a gate insulator.10. A method of forming a transistor device, said method comprising:forming an insulator over a substrate; forming a gate electrode abovesaid insulator; forming a pair of insulating spacers adjoining said gateelectrode; and converting a portion of said insulator into a metallicfilm, wherein said converting process only converts areas of saidinsulator not protected by said gate electrode and said insulatingspacers into said metallic film.
 11. The method of claim 10, whereinsaid insulator comprises a metal oxide film and wherein said convertingprocess comprises annealing said transistor device to remove oxygen fromsaid metal oxide film leaving said metallic film.
 12. The method ofclaim 10, wherein in said step of forming an insulator over a substrate,said insulator comprises a metal oxide material.
 13. The method of claim12, wherein said metal oxide material comprises one of a HfO_(x) and aZrO_(x).
 14. The method of claim 10, wherein in said step of converting,said portion of said insulator comprises a region above a source and adrain region of said substrate.
 15. The method of claim 10, furthercomprising siliciding said metallic film, wherein said step ofsiliciding occurs in a region above a source and a drain region of saidsubstrate.
 16. The method of claim 15, wherein said step of silicidingoccurs by one of an annealing process and a wet etching process.
 17. Themethod of claim 10, wherein said step of converting occurs by annealingin a reducing ambient environment.
 18. A method of forming a transistordevice, said method comprising: forming a metal oxide film over asubstrate; forming a gate electrode above said metal oxide film; forminga pair of insulating spacers adjoining said gate electrode; annealingsaid transistor device to drive oxygen from exposed regions of saidmetal oxide film not protected by said gate electrode and saidinsulating spacers, to produce a metallic film in said exposed regions;and converting said metallic film into one of a silicide and a salicidefilm.
 19. The method of claim 18, wherein said metal oxide filmcomprises one of a HfO_(x) and a ZrO_(X).
 20. The method of claim 18,wherein said exposed regions comprise areas above source and said drainregions of said substrate.
 21. The method of claim 18, wherein said stepof converting said metallic film into one of a silicide and a salicidefilm occurs in said exposed regions.
 22. The method of claim 18, whereinsaid annealing process occurs in a reducing ambient environment.
 23. Themethod of claim 18, wherein said step of converting occurs by one of asecond annealing process and a wet etching process.